Souleymane Dembele

Hardware Engineer | RTL, FPGA, SoC, and RF/Analog IC Design

Senior software engineer at a test-and-measurement company by day, building RTL and silicon the rest of the time.

Hi, I am Souleymane Dembele, a computer/hardware engineer in the Greater Seattle Area. I design across the stack: transistor-level RF/analog ICs, RTL and FPGA accelerators, computer architecture, and embedded firmware with custom RTOS work. My current focus is a custom GEMM accelerator on a Cyclone V SoC, the subject of my MS ECE thesis at the University of Washington Tacoma. The projects and write-ups below cover the hardware I build.

Selected Projects

GEMM Accelerator on Cyclone V SoC

GEMM Accelerator on Cyclone V SoC

Custom RTL matrix-multiply accelerator taken from SystemVerilog through Qsys integration to a full Linux bring-up (custom kernel, device-tree overlay, UIO binding, and user-space driver). An 8x8 heterogeneous systolic array runs INT8/INT16/INT32/FP16/FP32 in one multi-precision MAC. Fitter shows 112/112 DSP at 48% ALMs; a wide-port DMA fast path, operand-locality tuning (resident A, double-buffered B), and a hardware tile-row batch sequencer walk memory stall down 93% to 76% to 19% and take INT8 512^3 to 3.15 GOP/s at 50 MHz, about 27x an ARM A9 software reference, at 60% compute occupancy, bit-exact across all precisions (60/60 on-board tests).

SystemVerilog · FPGA · Cyclone V SoC · Linux driver · DSP

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CMOS Power Amplifier for GSM

CMOS Power Amplifier for GSM

Two-stage Class-AB power amplifier in TSMC 0.18um RF CMOS, designed in Cadence Virtuoso/SpectreRF with load-pull optimization. Targets the commercial Qorvo RF5110G and, in simulation, exceeds it: +38 dBm PSAT, 64.2% peak PAE, 33.2 dB gain, Ft of 26 GHz, with a 57% projected die-cost reduction versus GaAs HBT. (Simulation results, not silicon-measured.)

RF CMOS · Cadence Virtuoso · SpectreRF · Load-pull · 0.18um

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CMOS Ring Oscillator (0.18um)

CMOS Ring Oscillator (0.18um)

Five-stage transistor-level ring oscillator in the IBM 0.18um (cmrf7sf) CMOS process, designed, simulated, and laid out in Cadence Virtuoso. Met the 1 GHz +/- 100 MHz target (measured 1.06 GHz at N=5, Wn=82um, Wp=264um, Vdd=1.33V) with a DRC/LVS-clean layout.

0.18um CMOS · Cadence Virtuoso · DRC/LVS · Layout · Transient sim

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NES Emulator on FPGA

NES Emulator on FPGA

Cycle-aware NES emulator in Verilog built around a 6502 core, with custom PPU, APU, and VGA modules for video and audio. A UART path loads game ROMs and reads joystick input; memory-mapping logic handles cartridge data. Verified in Vivado/ISE and ModelSim for sprite rendering, frame rate, and audio sync.

Verilog · 6502 · PPU/APU · VGA · Vivado

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SystemVerilog Programmable Processor

SystemVerilog Programmable Processor

Programmable CPU in SystemVerilog (TCES330 course project). A control unit (instruction memory, program counter, instruction register, and FSM) drives a datapath (register file, ALU, data memory, and a 2:1 mux), tied together in a top-level processor. Executes NOOP/STORE/LOAD/ADD/SUB/HALT, runs on an FPGA with 7-segment output, and is verified with module and processor testbenches.

SystemVerilog · CPU · FSM · FPGA · Verification

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